Theoretically it is possible that first FF is still in metastable state when second FF samples the value and thus incorrect value can be sampled which will/can result in malfunction of the design (once in every MTBF years). The receiving logic will only use the output from second FF. If the first flip flop goes into metastable state because of setup/hold violations, the second flip flop give enough time for the first flop to come out of metastable state. One of the basic synchronizer circuit is a dual flip flop synchronizer (also called 2-FF synchronizer).ДЄ dual flip flop synchronizer is a circuit where two Flip Flops are connected back to back in the destination clock domain. Synchronizer circuits purpose is to protect the downstream logic to go into metastable state by minimize the probability of the metastability and increase MTBF. One of the most common way to handle Clock Domain Crossing (CDC) is usage of synchronizer circuits. Now as we understand metastability and its causes, we can look what are different techniques we can use to handle these situations in digital design. Without going into much of the math, the conclusion is that it is possible to calculate MTBF given that we know the data rate at the input of the FF and the clock frequency of the FF. Metastability occurrence of a given FF can be predicted by using a parameter called MTBF (Mean Time Between Failure) and is measured in years. This can lead the downstream FFs in the clk_B domain sample wrong value or worse go into metastable state as well.ДЇigure 3: Setup/hold violation leading to metastability The output of FF-B will go into metastable state and thus cannot settle to either 1 or 0. In picture below the output A of the FF-A changes very close to the pos-edge of the clk_B and thus violates the setup of the FF-B. Once an asynchronous signal is encountered into a clock domain, the setup and hold timings constraints are very unlikely to be met, and thus the FF can enter a metastable state. In figure 2 above, the signal A is asynchronous to destination clock domain, since there is no relation between clk_A and clk_B. Metastability cannot be avoided in digital design but can be handled properly by using different Clock Domain Crossing (CDC) techniques (discussed later) so that proper functionality of the design is intact.ДЇor proper operation of the flip flops, the inputs and clocks must satisfy the setup and hold requirements of the FFs. The signal will stabilize after some time but that depends on FF type and the PVT conditions. When applied into the digital design domain, it means that a FF can enter a state where output might not have reached to its final expected value and can oscillate between 0 or 1. In laymanвЂ™s terms, metastability is referred as unstable or intermediate state. However, designs which have two unrelated clocks (different clock frequencies) or clocks from two different sources (even with same frequency) are treated as multiple clock domain designs.ДЄnother fundamental concept to tackle the multiclock designs is metastability.

For example, a clock with frequency 10MHz and a divide by 2 clock driven from 10MHz clock are treated as a single clock domain design. To understand Clock Domain Crossing (CDC), we must understand some basics first.ДЄ clock domain is defined as part of the design that is driven by either one clock or more clocks that have related to each other. When data needs to be transferred between two different clock domains, it will appear to be asynchronous to the new clock domain. The modern SoCs, with so many dedicated data processing islands usually need to transfer data between these multiple clock domains (islands). We hope you will find this Clock Domain Crossing (CDC) tutorial useful for your ASIC designs.ДЇormally Clock Domain Crossing (CDC) in digital domain is defined as: вЂњThe process of passing a signal or vector (multi bit signal) from one clock domain to another clock domain.вЂќДЄ digital circuit with flip flops will always have clocks associated to it and circuits with only one clock domain are normally restricted to elementary school courses. This article provides an insight into Clock Domain Crossing (CDC) basics, and discuss the various techniques related to Clock Domain Crossing (CDC).

Type of domain iclock